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edition 2012-1-11 published by infineon technologies ag 81726 mnchen, germany ? infineon technologies ag 1/11/12. all rights reserved. attention please! the information given in this data sheet shall in no event be regarded as a guarantee of conditions or characteristics (?beschaffenheitsgarantie?). with respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, infineon technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation warranties of non-infringement of intellectual property rights of any third party. information for further information on technology, delivery terms and conditions and prices please contact your nearest infineon technologies office ( www.infineon.com ). warnings due to technical requirements components may contain dangerous substances. for information on the types in question please contact your nearest infineon technologies office. infineon technologies components may only be used in life-support devices or systems with the express written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered. for questions on technology, delivery and prices please contact the infineon technologies offices in germany or the infineon technologies companies and representatives worldwide: see our webpage at http:// www.infineon.com coolmos ? , coolset ? are trademarks of infineon technologies ag. coolset ? -f3r80 ICE3AR10080JZ revision history: 2012-1-11 datasheet version 2.2a previous version: 2.2 page subjects (major changes since last revision) 30 revise outline dimension for pg-dip-7 3, 7, 8, 12, 15, 16, 17, 18, 19, 20, 22 revise typo
type package marking v ds f osc r dson 1) 1) typ @ t=25c 230vac 15% 2) 2) calculated maximum input power rating at t a =50c, t i =125c and without copper area as heat sink. 85-265 vac 2) ICE3AR10080JZ pg-dip-7 3ar10080jz 800v 100khz 10.0 22w 15w ? ICE3AR10080JZ version 2.2a 3 11 jan 2012 off-line smps current mode controller with integrated 800v coolmos ? and startup cell (brownout & frequency jitter) in dip-7 pg-dip7 features ? 800v avalanche rugged coolmos ? with startup cell ? active burst mode for lowest standby power ? selectable entry and exit burst mode level ? 100khz internally fixed switching frequency with jittering feature ? auto restart protection for over load, open loop, vcc under voltage & over voltage and over temperature ? external auto-restart enable pin ? over temperature protection with 50c hysteresis ? built-in 10ms soft start ? built-in 20ms and extendable blanking time for short duration peak power ? propagation delay compensation for both maximum load and burst mode ? adjustable brownout feature ? overall tolerance of current limiting < 5% ? bicmos technology for low power consumption and wide vcc voltage range ? soft gate drive with 50 w turn on resistor description the ICE3AR10080JZ (coolset ? -f3r80) is an enhanced 800v mosfet version of ice3brxx65j (coolset ? -f3r 650v) in dip-7 package. the pwm controller is based on f3r 650v with some new and enhanced features. in particular it is a device running at 100khz, implemented with brownout features, installing 800v coolmos ? with startup cell and packaged into dip-7. it targets for the low power smps with increased mosfet voltage margin requirement such as off-line battery adapters, dvd r/w, dvd combi, blue ray, set top box, auxiliary power supply for pc and server, etc. in summary, the coolset ? f3r80 provides good voltage margin of mosfet, lowest standby power, selectable burst level, reduced output ripple during burst mode, reliable output with brownout feature, accurate maximum power control for both maximum power and burst power, low emi with frequency jittering and soft gate drive, built-in and flexible protections, etc. therefore, coolset ? f3r80 is a complete solution for the low power smps application. product highlights ? 800v avalanche rugged coolmos ? with startup cell ? active burst mode to reach the lowest standby power <100mw ? selectable entry and exit burst mode level ? adjustable blanking window for high load jumps ? frequency jitter and soft driving for low emi ? adjustable brownout feature ? auto restart protection for over load, over temperature, over voltage and external protection enable function ? pb-free lead plating; rohs compliant c vcc c bulk converter dc output + snubber power management pwm controller current mode 85 ... 270 vac typical application r sense fbb control unit - cs vcc startup cell precise low tolerance peak current limitation drain coolset ? -f3r80 (brownout & jitter) coolmos ? gnd r bo2 r bo1 active burst mode auto restart mode brownout mode bba
coolset ? -f3r80 ICE3AR10080JZ table of contents page version 2.2a 4 11 jan 2012 1 pin configuration and functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 1.1 pin configuration with pg-dip-7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 1.2 pin functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 2 representative blockdiagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 3.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 3.2 power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 3.3 improved current mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 3.3.1 pwm-op . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 3.3.2 pwm-comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 3.4 startup phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 3.5 pwm section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 3.5.1 oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 3.5.2 pwm-latch ff1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 3.5.3 gate driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 3.6 current limiting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 3.6.1 leading edge blanking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 3.6.2 propagation delay compensation (patented) . . . . . . . . . . . . . . . . . . . . .13 3.7 control unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 3.7.1 basic and extendable blanking mode . . . . . . . . . . . . . . . . . . . . . . . . . . .14 3.7.2 active burst mode (patented) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 3.7.2.1 selectable burst entry level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 3.7.2.2 entering active burst mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 3.7.2.3 working in active burst mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 3.7.2.4 leaving active burst mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 3.7.3 protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 3.7.3.1 vcc ovp, otp, external protection enable and vcc under voltage . . .18 3.7.3.2 over load, open loop protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 3.7.4 brownout mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 3.7.5 action sequence at bba pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 4 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 4.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 4.2 operating range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 4.3 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 4.3.1 supply section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 4.3.2 internal voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 4.3.3 pwm section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 4.3.4 soft start time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 4.3.5 control unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 4.3.6 current limiting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 4.3.7 coolmos ? section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
coolset ? -f3r80 ICE3AR10080JZ version 2.2a 5 11 jan 2012 5 coolmos ? performance characteristic . . . . . . . . . . . . . . . . . . . . . . . . . .27 6 input power curve . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 7 outline dimension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 8 marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 9 schematic for recommended pcb layout . . . . . . . . . . . . . . . . . . . . . . . .32
version 2.2a 6 11 jan 2012 coolset ? -f3r80 ICE3AR10080JZ pin configuration and functionality 1 pin configuration and functionality 1.1 pin configuration with pg-dip-7 figure 1 pin configuration pg-dip-7 (top view) 1.2 pin functionality bba (brownout, extended blanking time & auto- restart enable) the bba pin combines the functions of brownout, extendable blanking time for over load protection and the external auto-restart enable. the brownout feature is to stop the switching pulse when the input voltage is dropped to a preset low level. the extendable blanking time function is to extend the built-in 20 ms blanking time for over load protection by adding an external capacitor to ground. the external auto-restart enable function is an external access to stop the gate switching and force the ic to enter auto-restart mode. it is triggered by pulling the pin voltage to less than 0.4v. fbb (feedback & burst entry control) the fbb pin combines the feedback function and the burst entry/exit control. the regulation information is provided by the fbb pin to the internal protection unit and the internal pwm-comparator to control the duty cycle. the fbb-signal is the only control signal in case of light load at the active burst mode. the burst entry/ exit control provides an access to select the entry/exit burst mode level. cs (current sense) the current sense pin senses the voltage developed on the shunt resistor inserted in the source of the integrated coolmos ? . if cs reaches the internal threshold of the current limit comparator, the driver output is immediately switched off. furthermore the current information is provided for the pwm- comparator to realize the current mode. drain (drain of integrated coolmos ? ) pin drain is the connection to the drain of the integrated coolmos ? . vcc (power supply) the vcc pin is the positive supply of the ic. the operating range is between 10.5v and 25v. gnd (ground) the gnd pin is the ground of the controller. pin symbol function 1 bba brownout, extended blanking time & auto-restart enable 2 fbb feedback & burst entry/exit con- trol 3 cs current sense/ 800v coolmos ? source 4 n.c. not connected 5 drain 800v coolmos ? drain 6 - (no pin) 7 vcc controller supply voltage 8 gnd controller ground package pg-dip-7 1 7 8 4 3 2 5 gndbba fbb cs vcc n.c. drain
coolset ? -f3r80 ICE3AR10080JZ representative blockdiagram version 2.2a 7 11 jan 2012 2 representative blockdiagram figure 2 representative blockdiagram
version 2.2a 8 11 jan 2012 coolset ? -f3r80 ICE3AR10080JZ functional description 3 functional description all values which are used in the functional description are typical values. for calculating the worst cases the min/max values which can be found in section 4 electrical characteristics have to be considered. 3.1 introduction coolset ? -f3r80 brownout and jitter 800v version (ICE3AR10080JZ) is the enhanced version of the coolset ? -f3r 650v version (ice3brxx65j). it is particular good for high voltage margin low power smps application such as auxiliary power supply for pc and server. the major characteristics are that the ic is developed with 800v coolmos ? with start up cell, having adjustable brownout feature, running at 100khz switching frequency and packed in dip-7 package. it is derived from f3r 650v version. thus most of the good features are retained. besides, it includes some enhanced features and new features. the retained good features include bicmos technology to reduce power consumption and increase the vcc voltage range, cycle by cycle current mode control, built-in 10ms soft start to reduce the stress of switching elements during start up, built-in 20ms and extended blanking time for short period of peak power before entering protection, active burst mode for lowest standby power and propagation delay compensation for close power limit between high line and low line, frequency jittering for low emi performance, the built-in auto-restart mode protections for open loop, over load, vcc ovp, vcc under voltage, etc. and also the most flexible external auto-restart enable, etc. the enhanced features include narrowing the feedback voltage swing from 0.5v to 0.3v during burst mode so that the output voltage ripple can be reduced by 40%, reduction of the fast voltage fall time of the mosfet by increasing the soft turn-on time and addition of 50 w turn-on resistor, faster start up time by optimizing the vcc capacitor to 10uf and over temperature protection with 50c hysteresis. the new features include adjustable brownout for reliable output performance, selectable entry and exit burst mode so that smaller entry/exit power to burst mode or even no burst mode is possible and the propagation delay compensation for burst mode so that the entry/exit burst mode power is close between high line and low line. in summary, the coolset ? f3r80 provides good voltage margin of mosfet, lowest standby power, flexible burst level, reduced output ripple during burst mode, reliable output with brownout feature, accurate power limit for both maximum power and burst power, low emi with frequency jittering and soft gate drive, built-in and flexible protections, etc. therefore, coolset ? f3r80 is a complete solution for the low power smps application. 3.2 power management figure 3 power management the undervoltage lockout monitors the external supply voltage v vcc . when the smps is plugged to the main line the internal startup cell is biased and starts to charge the external capacitor c vcc which is connected to the vcc pin. this vcc charge current is controlled to 0.9ma by the startup cell. when the v vcc exceeds the on-threshold v ccon =17v the bias circuit are switched on. then the startup cell is switched off by the undervoltage lockout and therefore no power losses present due to the connection of the startup cell to the drain voltage. to avoid uncontrolled ringing at switch-on, a hysteresis start up voltage is implemented. the switch-off of the controller can only take place when v vcc falls below 10.5v after normal operation was entered. the maximum current consumption before the controller is activated is about 200ma. when v vcc falls below the off-threshold v ccoff =10.5v, the bias circuit is switched off and the soft start counter is reset. thus it ensures that at every startup cycle the soft start starts at zero. the internal bias circuit is switched off if auto restart mode is entered. the current consumption is then reduced to 320ma. internal bias voltage reference power management 5.0v undervoltage lockout 17v 10.5v power-down reset active burst mode auto restart mode startup cell vcc drain coolmos ? soft start block
coolset ? -f3r80 ICE3AR10080JZ functional description version 2.2a 9 11 jan 2012 once the malfunction condition is removed, this block will then turn back on. the recovery from auto restart mode does not require re-cycling the ac line. when active burst mode is entered, the internal bias is switched off most of the time but the voltage reference is kept alive in order to reduce the current consumption below 620ma. 3.3 improved current mode figure 4 current mode current mode means the duty cycle is controlled by the slope of the primary current. this is done by comparing the fbb signal with the amplified current sense signal. figure 5 pulse width modulation in case the amplified current sense signal exceeds the fbb signal the on-time t on of the driver is finished by resetting the pwm-latch (figure 5). the primary current is sensed by the external series resistor r sense inserted in the source of the integrated coolmos ? . by means of current mode regulation, the secondary output voltage is insensitive to the line variations. the current waveform slope will change with the line variation, which controls the duty cycle. the external r sense allows an individual adjustment of the maximum source current of the integrated coolmos ? . to improve the current mode during light load conditions the amplified current ramp of the pwm-op is superimposed on a voltage ramp, which is built by the switch t2, the voltage source v1 and a resistor r1 (see figure 6). every time the oscillator shuts down for maximum duty cycle limitation the switch t2 is closed by v osc . when the oscillator triggers the gate driver, t2 is opened so that the voltage ramp can start. figure 6 improved current mode in case of light load the amplified current ramp is too small to ensure a stable regulation. in that case the voltage ramp is a well defined signal for the comparison with the fbb-signal. the duty cycle is then controlled by the slope of the voltage ramp. by means of the time delay circuit which is triggered by the inverted v osc signal, the gate driver is switched-off until it reaches approximately 156ns delay time (figure x3.25 pwm op improved current mode 0.6v c8 pwm-latch cs fbb r s q q driver soft-start comparator t fbb amplified current signal t on t 0.6v driver pwm op 0.6v 10k ? oscillator c8 t 2 r 1 fbb pwm-latch v 1 gate driver voltage ramp v osc soft-start comparator time delay circuit (156ns) x3.25 pwm comparator
coolset ? -f3r80 ICE3AR10080JZ functional description version 2.2a 10 11 jan 2012 7). it allows the duty cycle to be reduced continuously till 0% by decreasing v fbb below that threshold. figure 7 light load conditions 3.3.1 pwm-op the input of the pwm-op is applied over the internal leading edge blanking to the external sense resistor r sense connected to pin cs. r sense converts the source current into a sense voltage. the sense voltage is amplified with a gain of 3.25 by pwm op. the output of the pwm-op is connected to the voltage source v 1 . the voltage ramp with the superimposed amplified current signal is fed into the positive inputs of the pwm- comparator c8 and the soft-start-comparator (figure 8). 3.3.2 pwm-comparator the pwm-comparator compares the sensed current signal of the integrated coolmos ? with the feedback signal v fbb (figure 8). v fbb is created by an external optocoupler or external transistor in combination with the internal pull-up resistor r fb and provides the load information of the feedback circuitry. when the amplified current signal of the integrated coolmos ? exceeds the signal v fbb the pwm-comparator switches off the gate driver. figure 8 pwm controlling 3.4 startup phase figure 9 soft start t t v osc 0.6v fbb t max. duty cycle gate driver voltage ramp 156ns time delay x3.25 pwm op improved current mode pwm comparator cs soft-start comparator 5v c8 0.6v fbb optocoupler r fb pwm-latch soft-start c om parator soft start & g 7 c 7 g ate d river 0.6v x3.25 pw m op c s soft start counter soft start s o f t s t a r t f i n i s h softs
coolset ? -f3r80 ICE3AR10080JZ functional description version 2.2a 11 11 jan 2012 in the startup phase, the ic provides a soft start period to control the primary current by means of a duty cycle limitation. the soft start function is a built-in function and it is controlled by an internal counter. . figure 10 soft start phase when the v vcc exceeds the on-threshold voltage, the ic starts the soft start mode (figure 10). the function is realized by an internal soft start resistor, an current sink and a counter. and the amplitude of the current sink is controlled by the counter (figure 11). figure 11 soft start circuit after the ic is switched on, the v softs voltage is controlled such that the voltage is increased step- wisely (32 steps) with the increase of the counts. the soft start counter would send a signal to the current sink control in every 300us such that the current sink decrease gradually and the duty ratio of the gate drive increases gradually. the soft start will be finished in 10ms (t soft-start ) after the ic is switched on. at the end of the soft start period, the current sink is switched off. within the soft start period, the duty cycle is increasing from zero to maximum gradually (see figure 12). figure 12 gate drive signal under soft-start phase in addition to start-up, soft-start is also activated at each restart attempt during auto restart. figure 13 start up phase v softs v softs2 v softs1 5v r softs soft start counter i 2i 4i softs 8i 32i t v softs32 v softs gate driver t t soft-start t t v s o fts t v s o fts 3 2 4.5v t s o ft-s ta rt v o u t v fb v o u t t s ta rt-u p
coolset ? -f3r80 ICE3AR10080JZ functional description version 2.2a 12 11 jan 2012 the start-up time t start-up before the converter output voltage v out is settled, must be shorter than the soft- start phase t soft-start (figure 13). by means of soft-start there is an effective minimization of current and voltage stresses on the integrated coolmos ? , the clamp circuit and the output rectifier and it helps to prevent saturation of the transformer during start-up. 3.5 pwm section figure 14 pwm section block 3.5.1 oscillator the oscillator generates a fixed frequency of 100khz with frequency jittering of 4% (which is 4khz) at a jittering period of 4ms. a capacitor, a current source and current sink which determine the frequency are integrated. the charging and discharging current of the implemented oscillator capacitor are internally trimmed in order to achieve a very accurate switching frequency. the ratio of controlled charge to discharge current is adjusted to reach a maximum duty cycle limitation of d max =0.75. once the soft start period is over and when the ic goes into normal operating mode, the switching frequency of the clock is varied by the control signal from the soft start block. then the switching frequency is varied in range of 100khz 4khz at period of 4ms. 3.5.2 pwm-latch ff1 the output of the oscillator block provides continuous pulse to the pwm-latch which turns on/off the integrated coolmos ? . after the pwm-latch is set, it is reset by the pwm comparator, the soft start comparator or the current -limit comparator. when it is in reset mode, the output of the driver is shut down immediately. 3.5.3 gate driver figure 15 gate driver the driver-stage is optimized to minimize emi and to provide high circuit efficiency. this is done by reducing the switch on slope when exceeding the integrated coolmos ? threshold. this is achieved by a slope control of the rising edge at the driver?s output (figure 16) and adding a 50 w gate turn on resistor (figure 15). thus the leading switch on spike is minimized. figure 16 gate rising slope furthermore the driver circuit is designed to eliminate cross conduction of the output stage. oscillator duty cycle max gate driver 0.75 clock & g9 1 g8 pwm section ff1 r s q soft start comparator pwm comparator current limiting coolmos ? gate frequency jitter soft start block vcc 1 pwm-latch coolmos ? gate driver gate 50 ? t (internal) v gate 4.6v typ. t = 160ns
coolset ? -f3r80 ICE3AR10080JZ functional description version 2.2a 13 11 jan 2012 during power up, when vcc is below the undervoltage lockout threshold v vccoff , the output of the gate driver is set to low in order to disable power transfer to the secondary side. 3.6 current limiting figure 17 current limiting block there is a cycle by cycle peak current limiting operation realized by the current-limit comparator c10. the source current of the integrated coolmos ? is sensed via an external sense resistor r sense . by means of r sense the source current is transformed to a sense voltage v sense which is fed into the pin cs. if the voltage v sense exceeds the internal threshold voltage v csth, the comparator c10 immediately turns off the gate drive by resetting the pwm latch ff1. a propagation delay compensation is added to support the immediate shut down of the integrated coolmos ? with very short propagation delay. thus the influence of the ac input voltage on the maximum output power can be reduced to minimal. this compensation applies to both the peak load and burst mode. in order to prevent the current limit from distortions caused by leading edge spikes, a leading edge blanking (leb) is integrated in the current sense path for the comparators c10, c12 and the pwm-op. the output of comparator c12 is activated by the gate g10 if active burst mode is entered. when it is activated, the current limiting is reduced to v csth_burst . this voltage level determines the maximum power level in active burst mode. 3.6.1 leading edge blanking figure 18 leading edge blanking whenever the integrated coolmos ? is switched on, a leading edge spike is generated due to the primary- side capacitances and reverse recovery time of the secondary-side rectifier. this spike can cause the gate drive to switch off unintentionally. in order to avoid a premature termination of the switching pulse, this spike is blanked out with a time constant of t leb = 220ns for normal load and t leb = 180ns for burst mode. 3.6.2 propagation delay compensation (patented) in case of overcurrent detection, there is always propagation delay to switch off the integrated coolmos ? . an overshoot of the peak current i peak is induced to the delay, which depends on the ratio of di/ dt of the peak current (figure 19). figure 19 current limiting the overshoot of signal2 is larger than of signal1 due to the steeper rising waveform. this change in the slope is depending on the ac input voltage. propagation delay compensation is integrated to current limiting c10 c12 & g10 propagation-delay compensation v csth pwm latch ff1 10k d1 1pf pwm-op propagation-delay compensation-burst v csth_burst cs leb 220ns leb 180ns s4 c5 v fb_burst fbb or g13 active burst mode t v sense v csth t leb = 220ns/180ns t i sense i limit t propagation delay i overshoot1 i peak1 signal1signal2 i overshoot2 i peak2
coolset ? -f3r80 ICE3AR10080JZ functional description version 2.2a 14 11 jan 2012 reduce the overshoot due to di/dt of the rising primary current. thus the propagation delay time between exceeding the current sense threshold v csth and the switching off of the integrated coolmos ? is compensated over temperature within a wide input range. current limiting is then very accurate. for example, i peak = 0.5a with r sense = 2. the current sense threshold is set to a static voltage level v csth =1v without propagation delay compensation. a current ramp of di/dt = 0.4a/s, or dv sense /dt = 0.8v/s, and a propagation delay time of t propagation delay =180ns leads to an i peak overshoot of 14.4%. with the propagation delay compensation, the overshoot is only around 2% (figure 20). figure 20 overcurrent shutdown the propagation delay compensation is realized by means of a dynamic threshold voltage v csth (figure 21). in case of a steeper slope the switch off of the driver is earlier to compensate the delay. figure 21 dynamic voltage threshold v csth similarly, the same concept of propagation delay compensation is also implemented in burst mode with reduced level, v csth_burst (figure 17). with this implementation, the entry and exit burst mode power can be very close between low line and high line input voltage. 3.7 control unit the control unit contains the functions for active burst mode and auto restart mode. the active burst mode and the auto restart mode both have 20ms internal blanking time. for the over load auto restart mode, the 20ms blanking time can be further extended by adding an external capacitor at bba pin. with the blanking time, the ic avoids entering into those two modes accidentally. those buffer time is very useful for the application which works in short duration of peak power occasionally. 3.7.1 basic and extendable blanking mode figure 22 basic and extendable blanking mode there are 2 kinds of blanking mode; basic mode and the extendable mode. the basic mode is a built-in 20ms blanking time while the extendable mode can extend this blanking time by connecting an external capacitor to the bba pin. for the extendable mode, the gate g5 remains blocked even though the 20ms blanking time is reached. after reaching the 20ms blanking time the counter is activated and the switch s1 is turned on to charge the voltage of bba pin by the constant current source, i chg_eb . when the voltage of bba pin hits 4.5v, which is sensed by comparator c11, the counter will increase the counter by 1. then it 0,9 0,95 1 1,05 1,1 1,15 1,2 1,25 1,3 0 0,2 0,4 0,6 0,8 1 1,2 1,4 1,6 1,8 2 with compensation without compensation dt dv sense s v ? s e n s e v v t v csth v osc signal1 signal2 v sense propagation delay max. duty cycle off time t c11 4.5v c3 0.9v c4 4.5v s1 control unit auto restart mode 5.0v fbb c bk spike blanking 3 0us i chg_eb s2 bba counter & g5 20ms blanking time r bo2 # 500 ? ct1
coolset ? -f3r80 ICE3AR10080JZ functional description version 2.2a 15 11 jan 2012 switches off the switch s1 and turns on the switch s2. the voltage at bba pin will be discharged through a 500 w resistor. when the voltage drops to 0.9v which is sensed by comparator c3, the switch s2 will be turned off and the switch s1 will be turned on. then the constant current i chg_eb will charge the c bk capacitor again. when the voltage at bba hits 4.5v which is sensed by comparator c11, the counter will increase the count to 2. the process repeats until it reaches total count of 256 (figure 23). then the counter will release a high output signal. when the and gate g5 detects both high signals at the inputs, it will activate the 30ms spike blanking circuit and finally the auto-restart mode will be activated. figure 23 waveform at extended blanking time for example, if c bk =0.1 m f, i chg_eb =720 ma extended blanking time = 256*(c bk *(4.5v-0.9v)/i chg_eb + c bk *500*ln(4.5/0.9)) = 148.6ms total blanking time = 20ms+ 148.6ms =168.6ms if there is a resistor r bo2 connected to bba pin, the effective charging current will be reduced. the blanking time will be increased. for example, if c bk =0.1 m f, i chg_eb =720 ma , r bo2 =12.8k w , i chg_eb ?=i chg_eb -(4.5v+0.9v)/(2*r bo2 )=509 ma extended blanking time = 256*(c bk *(4.5v-0.9v)/i chg_eb ? + c bk *500*ln(4.5/0.9)) = 201.6ms total blanking time = 20ms+201.6 = 221.6ms where i chg_eb ?=net charging current to c bk note: the above calculation does not include the effect of the brownout circuit where there is extra biasing current flowing from the input. that means the extended blanking time will be shortened with the line voltage change if brownout circuit is implemented. 3.7.2 active burst mode (patented) to increase the efficiency of the system at light load, the most effective way is to operate at burst mode. starting from coolset ? f3, the ic has been employing the active burst mode and it can achieve the lowest standby power. f3r80 adopts the same concept with some more innovative improvements to the feature. it includes the adjustable entry burst level, close power control between high line and low line and the smaller output ripple during burst mode. most of the burst mode design in the market will provide a fixed entry burst mode level which is a ratio to the maximum power of the design. f3r80 provides a more flexible level which can be selected externally. the provision also includes not entering burst mode. propagation delay is the major contributor for the power control variation for dcm flyback converter. it is proved to be effective in the maximum power control. f3r80 also apply the same concept in the burst mode. therefore, the entry and exit burst mode power is also finely controlled during burst mode. the feedback control swing during burst mode will affect the output ripple voltage directly. f3r80 reduces the swing from 0.5v to 0.3v. therefore, it would have around 40% improvement for the output ripple. figure 24 active burst mode the active burst mode is located in the control unit. figure 24 shows the related components. 3.7.2.1 selectable burst entry level the burst mode entry level can be selected by changing the different capacitor c fb at fbb pin. there are 4 levels to be selected with different capacitor which are targeted for 10%, 6.67%, 4.38% and 0% of the maximum input power. at the same time, the exit burst level are targeted to 20%, 13.3%, 9.6% and 0% of the maximum power accordingly. the corresponding capacitance range is from 6.8nf to 100pf. the below table is the recommended capacitance range for the entry and exit level with the c fb capacitor. normal operation extended blanking time auto restart v bba 0.9v 4.5v 256 counts c6a 3.5v c13 4.0v control unit internal bias c6b 3.2v & g11 active burst mode c5 20ms blanking time c fb c12 cs v csth_burst v fb_burst g10 & ff1 fbb current limiting burst detect and adjust
coolset ? -f3r80 ICE3AR10080JZ functional description version 2.2a 16 11 jan 2012 the selection is at the 1st 1ms of the uvlo ?on? (vcc > 17v) during the 1st start up but it does not detect in the subsequent re-start due to auto-restart protection. in case there is protection triggered such as auto restart enable or brownout before starts up, the detection will be held until the protection is removed. when the vcc reaches the uvlo ?on? in the 1st start up, the capacitor c fb at fbb pin is charged by a 5v voltage source through the r fb resistor. when the voltage at fbb pin hits 4.5v, the ff4 will be set, the switch s9 is turned ?on? and the counter will increase by 1. then the c fb is discharged through a 500 w resistor. after reaching 0.5v, the ff4 is reset and the switch s9 is turned ?off?. then the c fb capacitor is charged by the 5v voltage source again until it reaches 4.5v. the process repeats until the end of 1ms. then the detection is ended. after that, the total number of count in the counter is compared and the v fb-burst and the v cs_burst are selected accordingly (figure 25). figure 25 entry burst mode detection 3.7.2.2 entering active burst mode the fbb signal is kept monitoring by the comparator c5 (figure 24). during normal operation, the internal blanking time counter is reset to 0. when fbb signal falls below v fb_burst , it starts to count. when the counter reaches 20ms and fbb signal is still below v fb_burst , the system enters the active burst mode. this time window prevents a sudden entering into the active burst mode due to large load jumps. after entering active burst mode, a burst flag is set and the internal bias is switched off in order to reduce the current consumption of the ic to about 620ua. it needs the application to enforce the vcc voltage above the undervoltage lockout level of 10.5v such that the startup cell will not be switched on accidentally. or otherwise the power loss will increase drastically. the minimum vcc level during active burst mode depends on the load condition and the application. the lowest vcc level is reached at no load condition. 3.7.2.3 working in active burst mode after entering the active burst mode, the fbb voltage rises as vout starts to decrease, which is due to the inactive pwm section. the comparator c6a monitors the fbb signal. if the voltage level is larger than 3.5v, the internal circuit will be activated; the internal bias circuit resumes and starts to provide switching pulse. in active burst mode the gate g10 is released and the current limit is reduced to vcsth_burst (figure 2 and 24). in one hand, it can reduce the conduction loss and the other hand, it can reduce the audible noise. if the load at vout is still kept unchanged, the fbb signal will drop to 3.2v. at this level the c6b deactivates the internal circuit again by switching off the internal bias. the gate g11 is active again as the burst flag is set after entering active burst mode. in active burst mode, the fbb voltage is changing like a saw tooth between 3.2v and 3.5v (figure 26). 3.7.2.4 leaving active burst mode the fbb voltage will increase immediately if there is a high load jump. this is observed by the comparator c13 (figure 24). since the current limit is reduced to 31%~45% of the maximum current during active burst mode, it needs a certain load jump to rise the fbb signal to exceed 4.0v. at that time the comparator c5 resets the active burst mode control which in turn blocks the comparator c12 by the gate g10. the maximum current can then be resumed to stabilize v out. entry level exit level c fb % of p in_max v fb_burst % of p in_max v csth_burst >=6.8nf (5%,x7r) 10% 1.60v 20% 0.45v 1nf~2.2nf (1%,cog) 6.67% 1.42v 13.3% 0.37v 220pf~470pf (1%,cog) 4.38% 1.27v 9.6% 0.31v <=100pf (1%,cog) 0% never 0% always c19 c fb c20 0.5v 4.5v control unit s9 fbb 500 r fb counter comparator logic v csth_burst v fb_burst 1ms timer uvlo during 1 st startup 5v s q r uvlo ff4
coolset ? -f3r80 ICE3AR10080JZ functional description version 2.2a 17 11 jan 2012 figure 26 signals in active burst mode 3.7.3 protection modes the ic provides auto restart mode as the major protection feature. auto restart mode can prevent the smps from destructive states. there are 3 kinds of auto restart mode; normal auto restart mode, odd skip auto restart mode and non switch auto restart mode. odd skip auto restart mode is that there is no detect of fault and no switching pulse for the odd number restart cycle. at the even number of restart cycle the fault detect and soft start switching pulses maintained. if the fault persists, it would continue the auto-restart mode. however, if the fault is removed, it can release to normal operation only at the even number auto restart cycle (figure 27). figure 27 odd skip auto restart waveform non switch auto restart mode is similar to odd skip auto restart mode except the start up switching pulses are also suppressed at the even number of the restart cycle. the detection of fault still remains at the even number of the restart cycle. when the fault is removed, the ic will resume to normal operation at the even number of the restart cycle (figure 28). figure 28 non switch auto restart waveform the main purpose of the odd skip auto restart is to extend the restart time such that the power loss during auto restart protection can be reduced. this feature is particularly good for smaller vcc capacitor where the restart time is shorter. the following table lists the possible system failures and the corresponding protection modes. v fb_burst 3.5v 4.0v v fbb t t v csth_burst v csth v cs 10.5v v vcc t t 620ua i vcc t 3ma v out t 20ms blanking time current limit level during active burst mode 3.2v entering active burst mode blanking timer leaving active burst mode vcc over voltage (1) odd skip auto restart mode vcc over voltage (2) odd skip auto restart mode over load odd skip auto restart mode open loop odd skip auto restart mode 10.5v t v cs t v vcc 17v fault detected no detect startup and detect no detect 10.5v t v cs t v vcc 17v fault detected no detect startup and detect no detect no switching
coolset ? -f3r80 ICE3AR10080JZ functional description version 2.2a 18 11 jan 2012 3.7.3.1 vcc ovp, otp, external protection enable and vcc under voltage figure 29 vcc ovp, otp, external protection enable there are 2 types of vcc over voltage protection; vcc ovp (1) and vcc ovp (2). the vcc ovp (1) takes action only during the soft start period. the vcc ovp (2) takes the action in any conditions. vcc ovp (1) condition is when v vcc voltage is > 20.5v, v fbb voltage is > 4.5v and during soft start period, the ic enters into odd skip auto restart mode. this condition likely happens during start up at open loop fault. (figure 29). vcc ovp (2) condition is when v vcc voltage is > 25.5v, the ic enters into odd skip auto restart mode (figure 29). the over temperature protection otp is sensed inside the controller ic. the thermal shutdown block keeps on monitoring the junction temperature of the controller. after detecting a junction temperature higher than 130c, the ic will enter into the non switch auto restart mode. the f3r80 has also implemented with a 50c hysteresis. that means the ic can only be recovered when the controller junction temperature is dropped 50c lower than the over temperature trigger point (figure 29). the external auto restart enable feature can provide a flexibility to a customer?s self-defined protection feature. this function can be triggered by pulling down the v bba voltage to < 0.4v. or it can simply trigger the base pin of an external transistor, t ae at the bba pin. when this function is enabled, it will enter into the non switch auto restart mode. the gate drive is stopped and there is no switching pulse before it is recovered (figure 29). the vcc undervoltage and short opto-coupler will go into the normal auto restart mode inherently. in case of vcc undervoltage, the vcc voltage drops indefinitely. when it drops below the vcc under voltage lock out ?off? voltage (10.5v), the ic will turn off the ic and the startup cell will turn on again. then the vcc voltage will be charged up to uvlo ?on? voltage (17v) and the ic turns on again provided the startup cell charge up current is not drained by the fault. if the fault is not removed, the vcc will continue to drop until it hits uvlo ?off? voltage and the restart cycle repeats. short optocoupler can lead to vcc undervoltage because once the opto-coupler (transistor side) is shorted, the feedback voltage will drop to zero and there will be no switching pulse. then the vcc voltage will drop same as the vcc undervoltage. 3.7.3.2 over load, open loop protection figure 30 over load, open loop protection in case of overload or open loop, the v fbb voltage exceeds 4.5v which will be observed by comparator c4. then the built-in blanking time counter starts to count. when it reaches 20ms, the extended blanking time counter ct1 is activated. the switch s2 is turned on and the voltage at the bba pin will be discharged through 500 w resistor. when it drops to 0.9v, the switch s2 is turned off and the switch s1 is turned on. then a constant current source i chg_eb will start to charge up bba pin. when the voltage hits 4.5v which is monitored by comparator c11, the switch s1 is vcc undervoltage normal auto restart mode short optocoupler normal auto restart mode over temperature non switch auto restart mode external protection enable non switch auto restart mode c1 20.5v c4 4.5v voltage reference control unit auto restart mode reset v vcc < 10.5v fbb softs_period auto- restart enable signal t ae c9 0.4v stop gate drive spike blanking 30s thermal shutdown t j >130c bba auto restart mode & g1 vcc c2 120s blanking time 25.5v c11 4.5v c3 0.9v c4 4.5v s1 control unit 5.0v fbb c bk spike blanking 3 0us i chg_eb s2 bba counter & g5 20ms blanking time voltage reference auto restart mode reset v vcc < 10.5v auto restart mode r bo2 # 500 ? ct1
coolset ? -f3r80 ICE3AR10080JZ functional description version 2.2a 19 11 jan 2012 turned off and the count will increase by 1. then the switch s2 will turn on again and the voltage will drop to 0.9v and rise to 4.5v again. the count will then increase by 1 again. when the total count reaches 256, the counter ct1 will stop and it will release a high output signal. when both the input signals at and gate g5 is high, the odd skip auto restart mode is activated after the 30us spike blanking time (figure 30). the total blanking time depends on the addition of the built-in and the extended blanking time. if there is no c bk capacitor at bba pin, the count will finish within 0.1ms and the equivalent blanking time is just the built- in time of 20ms. however, if the c bk capacitor is big enough, it can be as long as 1s. if c bk is 0.1uf and i chg_eb is 720ua, the extendable blanking time is around 148.6ms and the total blanking time is 168.6ms. since the bba pin is a multi-function pin, it would share with different functions. the resistor r bo2 from brownout feature application may however affect the extendable blanking time (figure 30). thus it should take the r bo2 into the calculation of the extendable blanking time. for example the extended blanking time may be changed from 148.6ms to 201.6ms for without and having the 12.8k w r bo2 resistor. the list below shows one particular c bk , r bo2 vs blanking time. another factor to affect the extended blanking time is the input voltage through the r b01 and r b02 . it would, on the contrary, reduce the extended blanking time. 3.7.4 brownout mode when the ac input voltage is removed, the voltage at the bulk capacitor will fall. when it reaches a point that the system is greater than the system allowed maximum power, the system may go into over load protection. however, this kind of protection is not welcome for some of the applications such as auxiliary power for pc/server system because the output is in hiccup mode due to over load protection (auto restart mode). the brownout mode is to eliminate this phenomenon. the ic will sense the input voltage through the bulk capacitor to the bba pin by 2 potential divider resistors, r bo1 and r bo2 (figure 31). when the system is powered up, the bulk capacitor and the vcc capacitor are charged up at the same time. when the vcc voltage is charged to >7v, the brownout circuit start to operate (figure 31). since the uvlo is still at low level as the vcc voltage does not reach the 17v uvlo ?on? voltage. the nand gate g20 will release a low signal to the flip flop ff5 and the negative output of ff5 will release a high signal to turn on the switch s3. the constant load ld6 will start to draw constant current i chg_bo from the bba pin. that means the brownout mode is default ?on? during the system starts up. figure 31 brownout detection circuit once the system enters the brownout mode, there will be no switching pulse and the ic enters into another type auto-restart mode which is similar to the protection auto-restart mode but the ic will monitor the bba signal in each restart cycle (figure 32). figure 32 brownout mode waveform the voltage at bulk capacitor v bulk continues to increase and so is the voltage at bba. when the bba voltage reaches 0.9v, the output of opamp c14 will become low. through the inverter gate g21, the ?s? input of the flip flop ff5 is changed to high. then the negative output of ff5 is low. the brownout mode is then ?off? and the constant current load ld6 is also ?off? through the turn-off of the s3. the system will c bk r bo2 extended blanking time overall blanking time 0.1uf - 148.6ms 168.6ms 0.1uf 37.5k w 162.8ms 182.8ms 0.1uf 12.8k w 201.6ms 221.6ms c14 0.9v control unit brownout mode s3 bba r bo1 r bo2 v bulk i chg_bo 30 s~60 s blanking time uvlo q r s 5 s blanking time ff5 g20 g22 g21 ld6 10.5v t v cs t v vcc 17v brownout detected startup and detect bba voltage
coolset ? -f3r80 ICE3AR10080JZ functional description version 2.2a 20 11 jan 2012 turn on with soft start in the coming restart cycle when vcc reaches the vcc ?on? voltage 17v. when there is an input voltage drop, the bba voltage also drops. when the voltage at bba pin falls below 0.9v, the output of opamp c14 is changed to high. the inverter gate g22 will change the high input to low output. then the nand gate g22 will have a high output. the negative output of the flip flop ff5 is then become high. the constant load ld6 is ?on? again and the ic enters the brownout mode where the vcc swings between 10.5v and 17v without any switching pulse. the formula to calculate the r bo1 and r bo2 are as below. r bo1 =v hys /i chg_bo r bo2 =v ref_bo *r bo1 /(v bo_l -v ref_bo ) where v bo_l : input brownout voltage (low point); v hys : input brownout hysteresis voltage; v ref_bo : ic reference voltage for brownout; r bo1 and r bo2 : resistors divider from input voltage to bba pin for example, i chg_bo =10ua, v ref_bo =0.9v, case 1: if brownout voltage is 70vac on and 100vac off, then brownout voltage, v bo_l =100vdc, hysteresis voltage, v bo_hys =43vdc, r bo1 =4.3m w , r bo2 =39k w case 2: if brownout voltage is 100vac on and 120vac off, then brownout voltage, v bo_l =141vdc, hysteresis voltage, v bo_hys =28vdc, r bo1 =2.8m w , r bo2 =18k w case 3: if brownout voltage is 120vac on and 160vac off, then brownout voltage, v bo_l =169vdc, hysteresis voltage, v bo_hys =56vdc, r bo1 =5.6m w , r bo2 =30k w the summary is listed below. note: the above calculation assumes the tapping point (bulk capacitor) has a stable voltage with no ripple voltage. if there is ripple in the input voltage, it should take the highest voltage for the calculation; v bo_l + ripple voltage. besides that the low side brownout voltage v bo_l added with the ripple voltage at the tapping point should always be lower than the high side brownout voltage (v bo_h ); v bo_h > v bo_l + ripple voltage. otherwise, the brownout feature cannot work properly. in short, when there is a high load running in system before entering brownout, the input ripple voltage will increase and the brownout voltage will increase (v bo_l = v bo_l + ripple voltage) at the same time. if the v bo_hys is set too small and is close to the ripple voltage, then the brownout feature cannot work properly (v bo_l = v bo_h ). if the brownout feature is not needed, it needs to tie the bba pin to the vcc pin through a current limiting resistor, 500k w ~1m w . the bba pin cannot be in floating condition. if the brownout feature is disabled with a tie up resistor, there is a limitation of the capacitor c bk at the bba pin. it is as below. 3.7.5 action sequence at bba pin since there are 3 functions at the same bba pin; brownout, extended blanking time and the auto-restart enable, the actions of sequence are set as per the below table in case of several features happens simultaneously. the top row of the table is the first happened feature and the left column is the second happened feature. for example, case 1: the ?auto-restart enable? feature happened first and it follows with the ?extended blanking time? feature. then the ?auto-restart enable? feature will continue to hold and the ?extended blanking time? feature is ignored. case v bo_l v bo_h v bo_hys r bo1 r bo2 1 100v 143v 43v 4.3m w 39k w 2 141v 169v 28v 2.8m w 18k w 3 169v 225v 56v 5.6m w 30k w vcc tie up resistor c bk_max 1 500k w 0.47uf 2 1m w 0.22uf 1st 2nd auto-restart enable extended blanking time brownout auto-restart enable auto-restart enable auto-restart enable brownout extended blanking time auto-restart enable extended blanking time brownout brownout auto-restart enable extended blanking time brownout
coolset ? -f3r80 ICE3AR10080JZ functional description version 2.2a 21 11 jan 2012 case 2: the ?extended blanking time? feature happened first and it follows with the ?auto-restart enable? feature. then the ?auto-restart enable? feature will take the priority and the ?extended blanking time? feature is overridden. case 3: the ?extended blanking time? feature happened first and it follows with the ?brownout? feature. then the ?extended blanking time? feature will continue to work until it ends. after that if the over load fault is removed the ?brownout? feature takes the action. case 4: the ?brownout? feature happened first and it follows with the ?auto-restart enable? feature. then the ?brownout? feature will continue to work and the ?auto- restart enable? feature is ignored. one typical case happened is that the ?extended blanking time? feature happened first and it follows with the ?brownout? feature. if, however, the over load fault is removed before the end of the extended blanking time, the ?brownout? feature can take action only after 20ms buffer time.
coolset ? -f3r80 ICE3AR10080JZ electrical characteristics version 2.2a 22 11 jan 2012 4 electrical characteristics note: all voltages are measured with respect to ground (pin 8). the voltage levels are valid if other ratings are not violated. 4.1 absolute maximum ratings note: absolute maximum ratings are defined as ratings, which when being exceeded may lead to destruction of the integrated circuit. for the same reason make sure, that any capacitor that will be connected to pin 7 (vcc) is discharged before assembling the application circuit. t a =25 c unless otherwise specified. parameter symbol limit values unit remarks min. max. drain source voltage v ds - 800 v pulse drain current, t p limited by t jmax i d_puls - 1.10 a avalanche energy, repetitive t ar limited by max. t j =150c 1) 1) repetitive avalanche causes additional power losses that can be calculated as p av = e ar * f e ar - 0.011 mj avalanche current, repetitive t ar limited by max. t j =150c i ar - 0.44 a vcc supply voltage v vcc -0.3 27 v fbb voltage v fbb -0.3 5.5 v bba voltage v bba -0.3 5.5 v cs voltage v cs -0.3 5.5 v junction temperature t j -40 150 c controller & coolmos ? storage temperature t s -55 150 c thermal resistance junction -ambient r thja - 96 k/w soldering temperature, wavesoldering only allowed at leads t sold - 260 c 1.6mm (0.063in.) from case for 10s esd capability (incl. drain pin) v esd - 2 kv human body model 2) 2) according to eia/jesd22-a114-b (discharging a 100pf capacitor through a 1.5k w series resistor)
coolset ? -f3r80 ICE3AR10080JZ electrical characteristics version 2.2a 23 11 jan 2012 4.2 operating range note: within the operating range the ic operates as described in the functional description. 4.3 characteristics 4.3.1 supply section note: the electrical characteristics involve the spread of values within the specified supply voltage and junction temperature range t j from ? 25 c to 125 c. typical values represent the median values, which are related to 25c. if not otherwise stated, a supply voltage of v cc = 17 v is assumed. parameter symbol limit values unit remarks min. max. vcc supply voltage v vcc v vccoff 25 v max value limited due to vcc ovp junction temperature of controller t jcon -25 130 c max value limited due to thermal shut down of controller junction temperature of coolmos ? t jcoolmos -25 150 c parameter symbol limit values unit test condition min. typ. max. start up current i vccstart - 200 300 m a v vcc =16v vcc charge current i vcccharge1 - - 5.0 ma v vcc = 0v i vcccharge2 0.55 0.9 1.60 ma v vcc = 1v i vcccharge3 0.38 0.7 - ma v vcc =16v leakage current of start up cell and coolmo s ? i startleak - 0.2 50 m a v drain = 650v at t j =100c 1) 1) the parameter is not subjected to production test - verified by design/characterization supply current with inactive gate i vccsup1 - 1.9 3.2 ma supply current with active gate i vccsup2 - 3 4.4 ma i fbb = 0a supply current in auto restart mode with inactive gate i vccrestart - 320 - m a i fbb = 0a supply current in active burst mode with inactive gate i vccburst1 - 620 950 m a v fbb = 2.5v i vccburst2 - 620 950 m a v vcc = 11.5v, v fbb = 2.5v vcc turn-on threshold vcc turn-off threshold vcc turn-on/off hysteresis v vccon v vccoff v vcchys 16.0 9.8 - 17.0 10.5 6.5 18.0 11.2 - v v v
coolset ? -f3r80 ICE3AR10080JZ electrical characteristics version 2.2a 24 11 jan 2012 4.3.2 internal voltage reference 4.3.3 pwm section 4.3.4 soft start time parameter symbol limit values unit test condition min. typ. max. trimmed reference voltage v ref 4.90 5.00 5.10 v measured at pin fbb i fbb = 0 parameter symbol limit values unit test condition min. typ. max. fixed oscillator frequency f osc1 87 100 113 khz f osc2 92 100 108 khz t j = 25c frequency jittering range f jitter - 4.0 - khz t j = 25c frequency jittering period t jitter - 4.0 - ms t j = 25c max. duty cycle d max 0.70 0.75 0.80 min. duty cycle d min 0 - - v fbb < 0.3v pwm-op gain a v 3.05 3.25 3.45 voltage ramp offset v offset-ramp - 0.60 - v v fbb operating range min level v fbmin - 0.7 - v v fbb operating range max level v fbmax - - 4.3 v cs=1v, limited by comparator c4 1) 1) the parameter is not subjected to production test - verified by design/characterization fbb pull-up resistor r fb 9.0 15.4 22.0 k w parameter symbol limit values unit test condition min. typ. max. soft start time t ss - 10 - ms
coolset ? -f3r80 ICE3AR10080JZ electrical characteristics version 2.2a 25 11 jan 2012 4.3.5 control unit note: the trend of all the voltage levels in the control unit is the same regarding the deviation except v vccovp parameter symbol limit values unit test condition min. typ. max. brownout reference voltage for comparator c14 v bo_ref 0.80 0.90 1.00 v blanking time voltage lower limit for comparator c3 v bkc3 0.80 0.90 1.00 v blanking time voltage upper limit for comparator c11 v bkc11 4.28 4.50 4.72 v over load limit for comparator c4 v fbc4 4.28 4.50 4.72 v entry burst select high level for comparator c19 v fbc19 4.28 4.50 4.72 v entry burst select low level for comparator c20 v fbc20 0.40 0.50 0.60 v active burst mode entry level for comparator c5 10% p in_max v fb_burst1 1.51 1.60 1.69 v < 7 counts 6.67% p in_max v fb_burst2 1.34 1.42 1.50 v 8 ~ 39 counts 4.38% p in_max v fb_burst3 1.20 1.27 1.34 v 40 ~ 191 counts active burst mode high level for comparator c6a v fbc6a 3.35 3.50 3.65 v in active burst mode active burst mode low level for comparator c6b v fbc6b 3.06 3.20 3.34 v active burst mode level for comparator c13 v fbc13 3.85 4.00 4.15 v overvoltage detection limit for comparator c1 v vccovp1 19.5 20.5 21.5 v v fbb = 5v, during soft start overvoltage detection limit for comparator c2 v vccovp2 25.0 25.5 26.3 v auto-restart enable reference voltage for comparator c9 v ae 0.25 0.40 0.45 v charging current for extended blanking time i chg_eb 480 720 864 m a charging current for brownout i chg_bo 9.0 10.0 10.8 m a thermal shutdown 1) 1) the parameter is not subjected to production test - verified by design/characterization. the thermal shutdown temperature refers to the junction temperature of the controller. t jsd 130 140 150 c controller hysteresis for thermal shutdown 1) t jsd_hys - 50 - c built-in blanking time for overload protection or enter active burst mode t bk - 20 - ms timer for entry burst select t ebs - 1 - ms spike blanking time for auto-restart protection t spike - 30 - m s
coolset ? -f3r80 ICE3AR10080JZ electrical characteristics version 2.2a 26 11 jan 2012 and v vccpd 4.3.6 current limiting 4.3.7 coolmos ? section parameter symbol limit values unit test condition min. typ. max. peak current limitation (incl. propagation delay) v csth 0.99 1.06 1.13 v d v sense / d t = 0.6v/ m s (figure 20) peak current limitation during active burst mode 20% p in_max v csth_burst1 0.39 0.45 0.51 v < 7 counts 13.3% p in_max v csth_burst2 0.32 0.37 0.44 v 8 ~ 39 counts 9.6% p in_max v csth_burst3 0.25 0.31 0.37 v 40 ~ 191 counts leading edge blanking normal mode t leb_normal - 220 - ns burst mode t leb_burst - 180 - ns cs input bias current i csbias -1.5 -0.2 - m a v cs =0v parameter symbol limit values unit test condition min. typ. max. drain source breakdown voltage v (br)dss 800 870 - - - - v v t j = 25c t j = 110c 1) drain source on-resistance r dson - - - 10.0 22.4 27.3 11.1 24.6 30.0 w w w t j = 25c t j =125c 1) t j =150c 1) at i d = 0.27a 1) the parameter is not subjected to production test - verified by design/characterization effective output capacitance, energy related c o(er) - 3.3 - pf v ds = 0v to 480v rise time t rise - 30 2) 2) measured in a typical flyback converter application - ns fall time t fall - 30 2) - ns
coolset ? -f3r80 ICE3AR10080JZ coolmos ? performance characteristic version 2.2a 27 11 jan 2012 5 coolmos ? performance characteristic figure 33 safe operating area (soa) curve for ICE3AR10080JZ figure 34 soa temperature derating coefficient curve
coolset ? -f3r80 ICE3AR10080JZ coolmos ? performance characteristic version 2.2a 28 11 jan 2012 figure 35 power dissipation; p tot =f(t a ) figure 36 drain-source breakdown voltage; v br(dss) =f(t j ), i d =0.25ma
coolset ? -f3r80 ICE3AR10080JZ input power curve version 2.2a 29 11 jan 2012 6 input power curve two input power curves giving the typical input power versus ambient temperature are showed below; vin=85vac~265vac (figure 37) and vin=230vac+/-15% (figure 38). the curves are derived based on a typical discontinuous mode flyback model which considers either 60% maximum duty ratio or 150v maximum secondary to primary reflected voltage (higher priority). the calculation is based on no copper area as heatsink for the device. the input power already includes the power loss at input common mode choke, bridge rectifier and the coolmos.the device saturation current ( i d_puls @ t j =125c) is also considered. to estimate the output power of the device, it is simply multiplying the input power at a particular operating ambient temperature with the estimated efficiency for the application. for example, a wide range input voltage (figure 37), operating temperature is 50c, estimated efficiency is 85%, then the estimated output power is 12w (15w * 85%). figure 37 input power curve vin=85~265vac; p in =f(t a ) figure 38 input power curve vin=230vac+/-15%; p in =f(t a )
coolset ? -f3r80 ICE3AR10080JZ outline dimension version 2.2a 30 11 jan 2012 7 outline dimension figure 39 pg-dip-7 (pb-free lead plating plastic dual-in-line outline) pg-dip-7 (plastic dual in-line outline)
coolset ? -f3r80 ICE3AR10080JZ marking version 2.2a 31 11 jan 2012 8 marking figure 40 marking for ICE3AR10080JZ marking
coolset ? -f3r80 ICE3AR10080JZ schematic for recommended pcb layout version 2.2a 32 11 jan 2012 9 schematic for recommended pcb layout figure 41 schematic for recommended pcb layout general guideline for pcb layout design using f3 coolset (refer to figure 41): 1. ?star ground ?at bulk capacitor ground, c11: ?star ground ?means all primary dc grounds should be connected to the ground of bulk capacitor c11 separately in one point. it can reduce the switching noise going into the sensitive pins of the coolset device effectively. the primary dc grounds include the followings. a. dc ground of the primary auxiliary winding in power transformer, tr1, and ground of c16 and z11. b. dc ground of the current sense resistor, r12 c. dc ground of the coolset device, gnd pin of ic11; the signal grounds from c13, c14, c15 and collector of ic12 should be connected to the gnd pin of ic11 and then ?star ?connect to the bulk capacitor ground. d. dc ground from bridge rectifier, br1 e. dc ground from the bridging y-capacitor, c4 2. high voltage traces clearance: high voltage traces should keep enough spacing to the nearby traces. otherwise, arcing would incur. a. 400v traces (positive rail of bulk capacitor c11) to nearby trace: > 2.0mm b. 600v traces (drain voltage of coolset ic11) to nearby trace: > 2.5mm 3. filter capacitor close to the controller ground: filter capacitors, c13, c14 and c15 should be placed as close to the controller ground and the controller pin as possible so as to reduce the switching noise coupled into the controller. guideline for pcb layout design when >3kv lightning surge test applied (refer to figure 41): 1. add spark gap spark gap is a pair of saw-tooth like copper plate facing each other which can discharge the accumulated charge during surge test through the sharp point of the saw-tooth plate. a. spark gap 3 and spark gap 4, input common mode choke, l1: gap separation is around 1.5mm (no safety concern)
coolset ? -f3r80 ICE3AR10080JZ schematic for recommended pcb layout version 2.2a 33 11 jan 2012 b. spark gap 1 and spark gap 2, live / neutral to ground: these 2 spark gaps can be used when the lightning surge requirement is >6kv. 230vac input voltage application, the gap separation is around 5.5mm 115vac input voltage application, the gap separation is around 3mm 2. add y-capacitor (c2 and c3) in the live and neutral to ground even though it is a 2-pin input 3. add negative pulse clamping diode, d11 to the current sense resistor, r12: the negative pulse clamping diode can reduce the negative pulse going into the cs pin of the coolset and reduce the abnormal behavior of the coolset. the diode can be a fast speed diode such as in4148. the principle behind is to drain the high surge voltage from live/neutral to ground without passing through the sensitive components such as the primary controller, ic11.
qualit?t hat fr uns eine umfassende bedeutung. wir wollen allen ihren ansprchen in der bestm?glichen weise gerecht werden. es geht uns also nicht nur um die produktqualit?t ? unsere anstrengungen gelten gleicherma?en der lieferqualit?t und logistik, dem service und support sowie allen sonstigen beratungs- und betreuungsleistungen. dazu geh?rt eine bestimmte geisteshaltung unserer mitarbeiter. total quality im denken und handeln gegenber kollegen, lieferanten und ihnen, unserem kunden. unsere leitlinie ist jede aufgabe mit ?null fehlern? zu l?sen ? in offener sichtweise auch ber den eigenen arbeitsplatz hinaus ? und uns st?ndig zu verbessern. unternehmensweit orientieren wir uns dabei auch an ?top? (time optimized processes), um ihnen durch gr??ere schnelligkeit den entscheidenden wettbewerbsvorsprung zu verschaffen. geben sie uns die chance, hohe leistung durch umfassende qualit?t zu beweisen. wir werden sie berzeugen. quality takes on an allencompassing significance at semiconductor group. for us it means living up to each and every one of your demands in the best possible way. so we are not only concerned with product quality. we direct our efforts equally at quality of supply and logistics, service and support, as well as all the other ways in which we advise and attend to you. part of this is the very special attitude of our staff. total quality in thought and deed, towards co-workers, suppliers and you, our customer. our guideline is ?do everything with zero defects?, in an open manner that is demonstrated beyond your immediate workplace, and to constantly improve. throughout the corporation we also think in terms of time optimized processes (top), greater speed on our part to give you that decisive competitive edge. give us the chance to prove the best of performance through the best of quality ? you will be convinced. h t t p : / / w w w . i n f i n e o n . c o m total quality management published by infineon technologies ag

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